Multithreaded processors are processors that support simultaneous execution of multiple distinct instruction sequences or “threads.” Conventional threading techniques are described in, for example, M. J. Flynn, “Computer Architecture: Pipelined and Parallel Processor Design,” Jones and Bartlett Publishers, Boston, Mass., 1995, and G. A. Blaauw and Frederick P. Brooks, “Computer Architecture: Concepts and Evolution,” Addison-Wesley, Reading, Mass., 1997, both of which are incorporated by reference herein.
By way of example, a technique known as “barrel multithreading” allows each thread to issue an instruction in accordance with a specified fixed numeric sequence. For example, a processor with four threads, denoted Thread 0, Thread 1, Thread 2 and Thread 3, in accordance with barrel multithreading would allow the threads to issue instructions in the fixed numeric order Thread 0, Thread 1, Thread 2, Thread 3, Thread 0 and so on.
A problem with barrel multithreading and other existing threading techniques is that such techniques are generally not configured to permit arbitrary sequencing of thread instruction issuance, or if so configured require an excessive amount of hardware for their implementation.
Existing techniques are therefore unduly inflexible, and may place undesirable limitations on processor concurrency. Moreover, these techniques can contribute to blocking conditions and thus thread stalling, which adversely impacts processor performance.
A need therefore exists for improved threading techniques for use in a multithreaded processor.